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William Stallings Computer Organization and Architecture 8th Edition Instruction Level Parallelism and Superscalar Processors

What is Superscalar?o Common instructions (arithmetic, load/store, conditional branch) can be initiated and executed independently o Equally applicable to RISC & CISC o In practice usually RISC

Why Superscalar?

William Stallings Computer Organization and Architecture
8th Edition
Instruction Level Parallelism and Superscalar Processors

What is Superscalar?
• Common instructions (arithmetic, load/store, conditional branch) can be initiated and executed independently
• Equally applicable to RISC & CISC • In practice usually RISC

Why Superscalar?
• Most operations are on scalar quantities (see RISC notes)
• Improve these operations to get an overall improvement
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General Superscalar Organization

Superpipelined
• Many pipeline stages need less than half a clock cycle
• Double internal clock speed gets two tasks per external clock cycle
• Superscalar allows parallel fetch execute

Superscalar v Superpipeline

Limitations
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• Instruction level parallelism
• Compiler based optimisation
• Hardware techniques
• Limited by
— True data dependency
— Procedural dependency
— Resource conflicts
— Output dependency
— Antidependency
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• ADD r1, r2 (r1 := r1+r2;)
• MOVE r3,r1 (r3 := r1;)
• Can fetch and decode second instruction in parallel with first
• Can NOT execute second instruction until first is finished
True Data Dependency

Procedural Dependency
• Can not execute instructions after a 641 4481
branch in parallel with instructions before a branch
• Also, if instruction length is not fixed, instructions have to be decoded to find out how many fetches are needed
• This prevents simultaneous fetches su!ted

Resource Conflict
•
—
• —
Two or more instructions requiring access
to the same resource at the same time e.g. two arithmetic instructions
Can duplicate resources
e.g. have two arithmetic units

Effect of Dependencies

Design Issues
• — — —
• —
—
Instruction level parallelism
Instructions in a sequence are independent Execution can be overlapped
Governed by data and procedural dependency
Machine Parallelism
Ability to take advantage of instruction level
parallelism
Governed by number of parallel pipelines

Instruction Issue Policy
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• Order in which instructions are fetched
• Order in which instructions are executed
• Order in which instructions change registers and memory

Antidependency
• Write-write dependency
— R3:=R3 + R5; (I1)
— R4:=R3 + 1; (I2)
— R3:=R5 + 1; (I3)
— R7:=R3 + R4; (I4)
— I3 can not complete before I2 starts as I2
needs a value in R3 and I3 changes R3

Machine Parallelism
• Duplication of Resources
• Out of order issue
• Renaming
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• Not worth duplication functions without
register renaming
• Need instruction window large enough (more than 8)