Lakhasly

If the comparators bandwidth requirements are low enough, then an architecture, which differs from differential pairs, can be chosen as gain stage such as an open loop operational transconductance amplifier (OTA), which is shown in Fig.The analog voltage is sampled with the rising edge of the LATCH signal, which disconnects the inputs of the capacitors and connects the cross coupled structure to VDD and GND.Accordingly, the PCH device (MP1 or MP2) with the lower gate voltage will pull its drain voltage up. The outputs will be flipped to GND and VDD very quickly, which is shown in Fig.At 150 ns, where the input is positive, OUTP is pulled to VDD again in less than 3 ns. Both structures, the OTA and the cross coupled latch, have their advantage.The OTA provides sufficient gain, so that the signal will reach digital signal levels and a standard flipflop can be used to strobe the signal.During the sampling process, the capacitors (OUTP and OUTN) are charged to the input voltages INP and INN.A good alternative to the OTA is a differential cross-coupled latch, which is shown exemplarily in Fig.2.41.2.42.2.42.2.43).

If the comparators bandwidth requirements are low enough, then an architecture, which differs from differential pairs, can be chosen as gain stage such as an open loop operational transconductance amplifier (OTA), which is shown in Fig. 2.41.
The OTA provides sufficient gain, so that the signal will reach digital signal levels and a standard flipflop can be used to strobe the signal. In addition, it converts the fully differential input into a single ended output.
A good alternative to the OTA is a differential cross-coupled latch, which is shown exemplarily in Fig. 2.42. First, the signal LATCH is low, so that the cross- coupled latch is disconnected from the supplies VDD and GND. OUTP and OUTN are charged to the differential voltage of the inputs INP and INN. The input is connected to the output of the last differential pair of the comparator.
The analog voltage is sampled with the rising edge of the LATCH signal, which disconnects the inputs of the capacitors and connects the cross coupled structure to VDD and GND. The NCH device (MN1 or MN2) with the higher gate voltage will pull down its drain voltage. Accordingly, the PCH device (MP1 or MP2) with the lower gate voltage will pull its drain voltage up. The outputs will be flipped to GND and VDD very quickly, which is shown in Fig. 2.43 at the time points 50 and 150 ns. The first curve in Fig. 2.43 shows the differential input voltage to the cross coupled latch of Fig. 2.42. In the beginning, the latch is in the sampling phase, it triggers at 50 ns, starts sampling at 100 ns and triggers at 150 ns again. During the sampling process, the capacitors (OUTP and OUTN) are charged to the input voltages INP and INN. When the differential input (IN 1⁄4 INP!INN) is negative, then OUTP will be pulled to GND in less than 3 ns (see at time point 50 ns). At 150 ns, where the input is positive, OUTP is pulled to VDD again in less than 3 ns.
Both structures, the OTA and the cross coupled latch, have their advantage. The cross coupled latch is working without any DC current and saves power (see third curve of Fig. 2.43). The OTA is adding a low corner frequency and reduces the noise contribution of the comparator. This is particularly important, if the compar- ator is the most significant noise source in the SAR converter.